Cortex-M3 is an ARMv7-M CPU targeting the microcontrollers space. It supports the Thumb-2 instruction set, Memory Protection Unit (MPU but no MMU), integrated Nested Vectored Interrupt Controller (NVIC), timer.
Cortex-M3 supports two operating modes - Thread and Handler. The Thread mode can be privileged or unprivileged. The Handler mode is always privileged. At reset, the CPU starts in privileged Thread mode and switching to the Handler mode is done via an interrupt, exception or an explicit system call (the SVC instruction).
Cortex-M3 has two stacks - the main stack and the process stack. The Thread mode can use either the main or the process stacks. The Handler mode always uses the main stack. When taking an exception, the CPU automatically saves the state (R0-R3, R12, LR, ReturnAddress, xPSR) on the main stack. When returning from an exception, simply loading the exception LR into PC causes the state previously saved on the stack to be restored. Note that interrupts are not automatically disabled or enabled on exception entry or exit.
For more information, see the Cortex-M3 Technical Reference Manual and the ARMv7-M Architecture Reference Manual on the http://infocenter.arm.com website.